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r1lv0408d series 4m sram (512-kword 8-bit) rej03c0310-0100 rev.1.00 may.24.2007 description the r 1 lv0408d i s a 4-m b i t st at i c r a m organi zed 512-kword 8-bi t , fabri cat ed by r e nesas?s hi gh- performance 0.15 m c m os and tft t echnol ogi es. r 1 lv0408d seri es has real i zed hi gher densi t y, hi gher performance and l o w power consumpt i on. the r 1 lv0408d seri es offers l o w power st andby power di ssi pat i on; t h erefore, i t i s sui t a bl e for bat t e ry backup syst ems. it has packaged i n 32-pi n sop, 32- pi n tsop ii and 32-pi n stsop. features ? si ngl e 3 v suppl y: 2.7 v t o 3.6 v ? access t i m e: 55/ 70 ns (max) ? power di ssi pat i on: ? st andby: 3 w (t yp) ? equal access and cycle times ? c o mmon dat a i nput and out put . ? three state output ? directly ttl compatible. ? al l i nput s and out put s ? b a t t e ry backup operat i on. rev.1.00, may . 24.2007, page 1 of 12
r1lv0408d series ordering information type no. access time package r1lv0408dsp-5s % 5 5 n s r1lv0408dsp-7l % 7 0 n s 525-mil 32-pin plastic sop (32p2m-a) r1lv0408dsb-5s % 5 5 n s r1lv0408dsb-7l % 7 0 n s 400-mil 32-pin plastic tsop ii (32p3y-h) r1lv0408dsa-5s % 5 5 n s r1lv0408dsa-7l % 7 0 n s 8mm 13.4mm stsop (32p3k-b) % : temperature version; see table below. % t e m p e r a t u r e r a n g e r 0 to +70 c i ? 40 to + 8 5 c rev.1.00, may . 24.2007, page 2 of 12
r1lv0408d series pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 cc a11 a9 a8 a13 we# a18 a15 v a17 a16 a14 a12 a7 a6 a5 a4 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 v i/o2 i/o1 i/o0 a0 a1 a2 a3 ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 a17 we# a13 a8 a9 a11 oe# a10 cs# i/o7 i/o6 i/o5 i/o4 i/o3 cc (top view) 32-pin sop 32-pin tsop 32-pin stsop (top view) pin description pin name function a0 to a18 address input i/o0 to i/o7 data input/output cs# ( cs ) c h i p s e l e c t oe# ( oe ) o u t p u t e n a b l e we# ( we ) w r i t e e n a b l e v cc p o w e r s u p p l y v ss g r o u n d rev.1.00, may . 24.2007, page 3 of 12
r1lv0408d series block diagram ? i/o0 i/o7 cs# we# oe# a0 a1 a2 a3 a17 a5 v v cc ss row decoder memory matrix 2,048 2,048 column i/o column decoder input data control timing pulse generator read/write control a4 a18 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 lsb msb lsb msb rev.1.00, may . 24.2007, page 4 of 12
r1lv0408d series operation table w e # c s # o e # m o d e v cc current i/o0 to i/o7 ref. cycle h n o t s e l e c t e d i sb , i sb1 h i g h - z ? h l h output d i s a b l e i cc h i g h - z ? h l l r e a d i cc d o u t r e a d c y c l e l l h w r i t e i cc din write cycle (1) l l l w r i t e i cc din write cycle (2) note: h: v ih , l: v il , : v ih or v il absolute maximum ratings p a r a m e t e r s y m b o l v a l u e u n i t power supply voltage relative to v ss v cc ? 0.5 to +4.6 v terminal voltage on any pin relative to v ss v t ? 0.5 * 1 to v cc + 0 . 5 * 2 v power dissipation p t 0 . 7 w r ver. 0 to + 70 operating tem p e r a t u r e t o p r i ver. ? 40 to + 85 c storage temperature range tstg ? 65 to + 150 c r ver. 0 to + 70 storage temperature range under bias tbias i ver. ? 40 to + 8 5 c notes: 1. v t min: ? 3.0 v for pulse half-width 30 ns. 2. maximum voltage is + 4 .6 v. dc operating conditions p a r a m e t e r s y m b o l m i n t y p m a x u n i t v cc 2 . 7 3 . 0 3 . 6 v supply voltage v ss 0 0 0 v input high voltage v ih 2 . 2 ? v cc + 0.3 v input low voltage v il ? 0.3 * 1 ? 0 . 6 v r ver. ta 0 ? + 70 ambient temperature range i ver. ? 40 ? + 85 c note: 1. v il min: ? 3.0 v for pulse half-width 30 ns. rev.1.00, may . 24.2007, page 5 of 12
r1lv0408d series dc characteristics p a r a m e t e r s y m b o l m i n t y p max u nit t est conditions input leakage current |i li | ? ? 1 a vin = v ss to v cc output leakage current |i lo | ? ? 1 a cs# = v ih or oe# = v ih or we# = v il or v i/o = v ss to v cc operating current i cc ? ? 10 ma cs# = v il , others = v ih / v il , i i/o = 0 ma i cc1 ? ? 25 ma min. cycle, duty = 100%, cs# = v il , others = v ih /v il i i/o = 0 ma average operating current i cc2 ? ? 5 ma cycle time = 1 s, duty = 100%, i i/o = 0 ma, cs# 0.2 v, v ih v cc ? 0.2 v, v il 0.2 v standby current i sb ? 0.1 * 1 0.3 ma cs# = v ih to +85 c i sb1 ? ? 1 0 a to +70 c i sb1 ? ? 8 a to +40 c i sb1 ? ? 3 a ? 5s % to +25 c i sb1 ? 1 * 1 2 . 5 a to +85 c i sb1 ? ? 2 0 a to +70 c i sb1 ? ? 1 6 a to +40 c i sb1 ? ? 1 0 a standby current ? 7l % to +25 c i sb1 ? 1 * 1 1 0 a vin 0 v, cs# v cc ? 0.2 v average values v ol ? ? 0.4 v i ol = 2.1 ma output low voltage v ol 2 ? ? 0.2 v i ol = 100 a v oh 2 . 4 ? ? v i oh = ? 1.0 ma output high voltage v oh2 v cc ? 0.2 ? ? v i oh = ? 0.1 ma note: 1. typical values are at v cc = 3 . 0 v, ta = +2 5 c and specified loadi ng, and not guaranteed. capacitance (ta = +25 c , f = 1.0 m h z) p a r a m e t e r s y m b o l m i n t y p m a x u n i t test conditions note input capacitance cin ? ? 8 pf vin = 0 v 1 input/output capacitance c i/o ? ? 1 0 p f v i/o = 0 v 1 note: 1. this parameter is sampled and not 100% tested. rev.1.00, may . 24.2007, page 6 of 12
r1lv0408d series ac characteristics (ta = 0 to + 70 c / ? 40 t o +85 c, v cc = 2.7 v t o 3.6 v) test conditions ? input pul se l e vel s : v il = 0.4 v, v ih = 2.4 v ? input ri se and fal l t i me: 5 ns ? input and out put t i m i ng reference l e vel s : 1.5 v ? output load: 1 ttl gate + c l (50 pf) (r 1lv0408d-5s % ) 1 ttl gate + c l (100 pf) (r 1lv0408d-7l%) (incl udi ng scope and j i g) note: temperature range depends on r/i-ve rsion. please see table on page 2. read cycl e r1lv0408d - 5 s % - 7 l % p a r a m e t e r s y m b o l m i n m a x m i n m a x u n i t n o t e s read cycle time t rc 5 5 ? ? ? ? ? ? ? ? ? ? ? ? ? ? rev.1.00, may . 24.2007, page 7 of 12
r1lv0408d series write cycle r1lv0408d - 5 s % - 7 l % p a r a m e t e r s y m b o l m i n m a x m i n m a x u n i t n o t e s write cycle time t wc 5 5 ? 7 0 ? n s chip selection to end of write t cw 5 0 ? 6 0 ? n s 4 address setup time t as 0 ? 0 ? n s 5 address valid to end of write t aw 5 0 ? 6 0 ? n s w r ite pulse width t wp 4 0 ? 5 0 ? n s 3 , 1 2 write recovery time t wr 0 ? 0 ? n s 6 w r ite to output in high-z t whz 0 2 0 0 2 5 n s 1 , 2 , 7 data to write time overlap t dw 2 5 ? 3 0 ? n s data hold from write time t dh 0 ? 0 ? n s output active from end of write t ow 5 ? 5 ? n s 2 output disable to output in high-z t ohz 0 2 0 0 2 5 n s 1 , 2 , 7 notes: 1. t hz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs# and a low w e #. a write begins at the later transition of cs# going low or w e # going low. a write ends at the earlier transition of cs# going high or w e # going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs# going low to the end of write. 5. t as is measured from the address va lid to the beginning of write. 6. t wr is measured from the earlier of we# or cs# going high to the end of write cycle. 7. during this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. if the cs# low transition occurs simultaneously with the w e # low transition or after the w e # transition, the output remain in a high impedance state. 9. dout is the same phase of t he write data of this write cycle. 10. dout is the r ead data of next address. 11. if cs# is low during this period, i/o pins are in the output state. theref ore, the input signals of the opposite phase to the outputs must not be applied to them. 12. in the write cycle with oe# low fixed, t wp must satisfy the following equat ion to avoid a problem of data bus contention. t wp t dw min + t whz max rev.1.00, may . 24.2007, page 8 of 12
r1lv0408d series timing waveform read t i mi ng waveform (we# = v ih ) t aa t co t rc t lz t oe t olz t hz t ohz valid data valid address high impedance address cs# oe# dout t oh rev.1.00, may . 24.2007, page 9 of 12
r1lv0408d series write timing waveform (1) (oe# c l ock) t wc t cw t wp t as t ohz t dw t dh t aw t wr *8 address oe# cs# we# dout din valid data valid address high impedance rev.1.00, may . 24.2007, page 10 of 12
r1lv0408d series write timing waveform (2) (oe# low fixed) address cs# we# dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *11 *9 *10 *8 valid data valid address high impedance rev.1.00, may . 24.2007, page 11 of 12
r1lv0408d series rev.1.00, may . 24.2007, page 12 of 12 low v cc data retention characteristics (ta = 0 to +70 c / ? 40 t o +85 c) p a r a m e t e r s y m b o l min t y p max u nit t est conditions v cc for data retention v dr 2 ? ? v cs# v cc ? 0.2 v, vin 0 v to +85 c i ccdr ? ? 1 0 a to +70 c i ccdr ? ? 8 a to +40 c i ccdr ? ? 3 a ? 5s % to +25 c i ccdr ? 1 * 1 2 . 5 a to +85 c i ccdr ? ? 2 0 a to +70 c i ccdr ? ? 16 a to +40 c i ccdr ? ? 1 0 a data retention current ? 7l % to +25 c i ccdr ? 1 * 1 1 0 a v cc = 3.0 v, vin 0 v cs# v cc ? 0.2 v average values chip deselect to data retention time t cdr 0 ? ? n s operation recovery time t r 5 ? ? m s see retention waveform v cc 2.7 v 2.2 v 0 v cs# t cdr t r cs# v cc ? 0.2 v v dr data retention mode note: 1. typical values are at v cc = 3 . 0 v, ta = +2 5 c and specified loadi ng, and not guaranteed. low v cc data retention timing waveform (cs# controlled)
revision history r1lv0408d series data sheet contents of modification rev. date page description 0.01 dec. 25, 2006 ?
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